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Wafer Processing

The 3DGS patented manufacturing process is simple, elegant and consistent with traditional semiconductor techniques. Photosensitive glass ceramic wafers similar in size to semiconductor silicon wafers are sourced from 3DGS glass supplier partners. During the 3DGS process, the wafers are masked, exposed to UV light, thermally processed, chemically etched, metallized and plated.

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Step 1

Start with blank APEX® Glass (Wafer or Panel), then expose and pattern

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Steps 2 and 3

Bake the wafer to convert exposed regions into ceramic.

Wet etch ceramic regions to form 3D

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Step 4

Plate open 3D vias and cavities with Copper

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Step 5

Plating frontside and backside interconnections

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Steps 6 and 7

Create IPD by metal sputtering, then

PECVD SiOx, SiNx, TaN; ALD Al2O3, HFO, etc.

The process is high-volume, scalable, repeatable, precise and limitless in design possibilities. Due to its scalability and high-volume compatibility, the process delivers time-efficient, cost-saving benefits to customers.